IS200TREGH1A

IS200TREGH1A is a Turbine Emergency Trip Terminal Board manufactured and designed by General Electric as part of the Mark VI Series used in Speedtronic Control Systems. The I/O controller manages TREG, which powers three emergency trip solenoids. The TREG and TRPG terminal boards can connect up to three trip solenoids. TREG supplies the solenoids with the positive side of the dc power, while TRPG supplies the negative side. The I/O controller controls the 12 relays on TREG, nine of which form three groups of three to vote inputs controlling the three trip solenoids, as well as emergency Overspeed protection and emergency stop operations. There are a number of board types as follows:

• The H1B version is utilized in place of the H1A version for new production.
• The main version for 125 V dc applications is H1B. On the board, redundant power is created by bimodally combining control power from the JX1, JY1, and JZ1 connectors to power the economizing relays and status feedback circuits. The trip relay circuits ensure power isolation.
• Applications requiring 24 V dc use H2B. Other traits are identical to those of H1B.
• A modified form of H1B called H3B is used in systems with redundant TREG boards. The JX1 connector is the only source of power for the feedback circuit and the cost-saving relay.
• H4B is a modified form of H1B that is used in TREG board redundancy systems. The JY1 connector is the only source of power for the feedback circuit and the cost-saving relay.
• A modified variant of H1B called H5B is used in systems with redundant TREG boards. The JZ1 connector is the only source of power for the feedback circuit and the cost-saving relay.

Typically, one H3B and one H4B board are used in tandem in redundant TREG applications. To preserve the control power separation built into these systems, system repairs must be carried out using the appropriate type of board.

MARK VI SYSTEMS: The TPRO interfaces with the TREG terminal board in Mark VI systems. TREG and the TPRO module are connected by cables with molded plugs.
MARK VIe SYSTEMS: TREG is managed by the PPRO pack on SPRO on Mark VIe systems. The D-type connectors on SPRO accept the PPRO I/O packs for insertion. TREG and the SPRO board are connected by cables with molded plugs.

INSTALLATION:

The first I/O terminal block is directly wired to the three trip solenoids, the economizing resistors, and the emergency stop. The second terminal block can accept wiring for up to seven trip interlocks.

OPERATION:

The J2 power cable and the trip solenoids are the only connections to the control modules since the I/O controller controls all aspects of TREG. When a turbine trips in simplex systems, a third cable transmits a trip signal from J1 to the TSVO terminal board, which operates a servo valve clamp.

SOLENOID TRIP SETS:

The controller's application software is used to launch tests of the trip solenoids. Through the PTR relays from the controller or the ETR relays from the protection module, each trip solenoid can be manually tripped one at a time during online tests. In order to provide a reliable indication that the solenoid has tripped, a contact from each solenoid circuit is linked back as a contact input. Additionally, primary and emergency offline Overspeed tests are offered for the purpose of verifying actual trips that have been affected by software-simulated Overspeed conditions.

DIAGNOSTICS:

The TREG board and linked devices are subjected to diagnostic tests by the I/O controller. The diagnostics cover the solenoid voltage source, the trip relay driver and contact feedbacks, the economizer relay driver and contact feedbacks, the K25A relay driver and coil, the servo clamp relay driver and contact feedback, and the economizer relay driver and contact feedbacks. A fault is produced if even one of these deviates from the desired value.

The I/O controller queries the ID devices on the TREG connections JX1, JY1, and JZ1. The terminal board serial number, board type, revision number, and plug location are all encoded on the read-only ID device chip. A hardware incompatibility fault is produced when a mismatch is found while reading the chip by the I/O board.